As technology advances, there is a need for logic components implemented with power management functions. However, such components require effective electrostatic discharge (ESD) protection in order to function properly. A gate-grounded metal oxide semiconductor (GGMOS) transistor serves as one of the potential ESD protection devices for these components. For example, n-type GGMOS (GGNMOS) transistors are used as ESD protection devices. However, conventional GGNMOS transistors suffer from several issues, such as early latch up and low holding/snapback voltage. In addition, GGNMOS transistors consume a large area, resulting in a large integrated circuit (IC). This results in scalability issues as well as increased manufacturing costs.
In view of the foregoing, it is desirable to provide a compact GGMOS transistor with improved ESD protection performance without a large footprint.